DSPIC30F IC unlock

Posted by

IC unlockĀ may occur when second instructions are executed. In this case, second instructions and additional stopping cycles are allowed to execute before ISR. In this way, the stopping period associated with the second instructions will normally execute. However, the stopping cycle will actually be embedded in the sequence of abnormal processes. If a normal double cycle instruction is interrupted, the abnormal process will continue.
Three, instruction stop cycle and process change instruction
CALL and RCALL instructions use W15 to write to the stack, and if the source read by the next instruction uses W15, execution of the instructions may therefore be forced to stop before the next instruction. RETFIE and RETURN instructions can never be forced to stop before the next instruction, because these instructions can only perform read operations. However, users should be aware that the RETLW instruction can force a stop because it writes to the W register in the last cycle. Because GOTO and transfer instructions do not perform write operations, they can never force instruction to stop.
Four, instruction stop and DO and REPEAT cycles.
In addition to increasing the instruction stop cycle, RAW data dependency does not affect the work of DO or REPEAT loops. The prefetching instructions in the REPEAT loop will not change until the loop completes or occurs. Although register correlation checks cross instruction boundaries, dsPIC30F actually compares the source and destination addresses of the same instruction in a REPEAT loop. The last instruction of the DO loop prefetches the instruction at the start address of the loop or the next instruction (outside the loop). The decision to stop the instruction is made by the last instruction of the loop and the contents of the prefetch instruction.
Five, instruction stop and program space visibility (PSV)
When the program space (PS) is mapped to the data space by enabling the PSV (CORCON < 2 >) bit, and the X space EA is within the visible program space range, the read or write cycle is redirected to the address in the program space. It takes up to 3 instruction cycles to access data from program space. Instruction operations in PSV address space, like any other instruction, are affected by RAW data correlation and subsequent instruction stops.

Leave a Reply

Your email address will not be published. Required fields are marked *