dsPIC30F3011 chip decryption

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High performance modified RISC CPU:
Improved Harvard architecture
C compiler optimized instruction set architecture
Flexible addressing mode
• 84 basic instructions
24 bit wide instruction, 16 bit width data path.
• 144 KB on chip flash program space
(instruction word)
• 8 bytes of on-chip data RAM
• 4 byte nonvolatile data EEPROM
Work up to 30 MIPS:
– external clock input from DC to 40 MHz
– input for 4 MHz-10 MHz oscillator
Active phase locked loop (4X, 8X, 16X)
• 44 interrupt sources
– 5 external interrupt sources
– 8 users, the priority of each choice.
Interruption source
– 4 processor trap sources
• 16 x 16 bit work register array
The characteristics of the DSP engine are:
Double access data
Accumulator write back for DSP operation
Module and bit inversion addressing mode
Two, 40 bit optional wide battery
Saturation logic
• 17 bit x 17 bit single cycle hardware decimal /
Integer multiplier
• all DSP instruction cycles
+ 16 bit single cycle transition
Peripheral features:
• high pour / pull current I / O pin: 25 mA/25 Ma
• timer module with programmable prescaler:
– 5 16 bit timer / counters;
16 to 32 timer module timer
16 bit capture input function
• 16 bit comparison / PWM output function
• 3 line SPI module (support 4 frame mode)
The I2CTM module supports multiple modes.
And 7-bit/10-bit solution
• 2 UART modules, FIFO buffers
2 CAN modules, 2.0B compatible
The features of the motor control PWM module are:
• 8 PWM output channels
Complementary or independent output
Pattern
– edge and center alignment mode
• 4 duty cycle generators
Dedicated time base
Programmable output polarity
• dead time control for complementary mode
Manual output control
A / D conversion triggering
Quadrature encoder interface module
Characteristic:
A phase, B phase and index pulse input.
• 16 position up / down position counters
Counting direction state
Position measurement (x2 and x4) mode
• programmable digital noise filter on input terminals
• standby 16 bit timer / counter mode
Position counter full / underflow interrupt

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