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PCB design technology

Description

In the PCB design technology, we can’t simply whip up quickly, create a library, input the schematic, and then process the layout, leaving the problem to the end, we always have such a loophole in the PCB design. We may also have technical errors in the library, which can lead to mismatches in the subsequent design process. We may cause signal integrity issues and manufacturing issues due to violations. In any case, these and many other issues will make progress behind schedule.
Online DRC allows PCB designers to quickly complete etching and dynamically avoid errors by the system, so in the design finishing phase, only a small amount of cleaning is required when necessary, sometimes not at all. With these methods, PCB designers can focus on design, quality, and innovation without having to spend time checking for errors during the final stages of the design cycle.
The following are eight steps to easily set up PCB design constraints.

  1. Enter all the usual spacing required for the design. This information is best developed as a benchmark for all future designs and turned into templates to avoid having to re-enter this data for each design. It’s also a great way to develop package spacing requirements for your X, Y, and Z axes, allowing your system to flag any issues during 2D and 3D layouts.
  2. Check the product description of the most relevant components used and check the pin spacing and dimensions. This will help you determine the minimum rules required for the width and spacing of the traces. Keep in mind that you should maximize the width and spacing of the traces to achieve the best in terms of manufacturability (DFM) so that your design will achieve the best quality after it is put into production.
  3. Collect requirements for critical circuits (DDR3/4, PCI-X, etc.), such as other spacing issues, topology, delay, and impedance information, to prepare for building your constraints.
  4. Set minimum and maximum constraints for each of these requirements. They will serve as your default constraint benchmark, and all other constraint spacing classes developed in the future will be used as a benchmark.
  5. Create additional constraint spacing for other known conditions, such as high speed 3W constraints.
  6. Once all of these constraints are known and set, create a scenario or rule area for the exception. Each scenario is propagated through a default scheme, so it’s important to create exceptions after all constraints are known and set.
  7. Develop network classes for specific critical circuits and create the class-to-class spacing required to provide the spacing requirements between the various key classes.
  8. Develop constraint classes for differential pairs, topologies, timing, delay matching, and tolerances for specific critical networks.

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